1074 search results - page 212 / 215 » Parallelizing post-placement timing optimization |
HPCA
2008
IEEE
14 years 8 months ago
2008
IEEE
Cache partitioning and sharing is critical to the effective utilization of multicore processors. However, almost all existing studies have been evaluated by simulation that often ...
ICDCS
2009
IEEE
14 years 4 months ago
2009
IEEE
A number of network path delay, loss, or bandwidth inference mechanisms have been proposed over the past decade. Concurrently, several network measurement services have been deplo...
ICCAD
2006
IEEE
14 years 4 months ago
2006
IEEE
A dynamically reconfigurable processor (DRP) is designed to achieve high area efficiency by switching reconfigurable data paths dynamically. Our DRP architecture has a stand alone...
VEE
2009
ACM
14 years 2 months ago
2009
ACM
r of high-level languages lies in their abstraction over hardware and software complexity, leading to greater security, better reliability, and lower development costs. However, o...
EDBT
2009
ACM
14 years 2 months ago
2009
ACM
Database storage managers have long been able to efficiently handle multiple concurrent requests. Until recently, however, a computer contained only a few single-core CPUs, and th...