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IPCCC
2006
IEEE
14 years 2 months ago
OS-aware tuning: improving instruction cache energy efficiency on system workloads
Low power has been considered as an important issue in instruction cache (I-cache) designs. Several studies have shown that the I-cache can be tuned to reduce power. These techniq...
Tao Li, Lizy K. John
ISCA
2006
IEEE
154views Hardware» more  ISCA 2006»
14 years 2 months ago
SODA: A Low-power Architecture For Software Radio
The physical layer of most wireless protocols is traditionally implemented in custom hardware to satisfy the heavy computational requirements while keeping power consumption to a ...
Yuan Lin, Hyunseok Lee, Mark Woh, Yoav Harel, Scot...
RTCSA
2006
IEEE
14 years 2 months ago
Integrating Compiler and System Toolkit Flow for Embedded VLIW DSP Processors
To support high-performance and low-power for multimedia applications and for hand-held devices, embedded VLIW DSP processors are of research focus. With the tight resource constr...
Chi Wu, Kun-Yuan Hsieh, Yung-Chia Lin, Chung-Ju Wu...
CLUSTER
2005
IEEE
14 years 2 months ago
Minimizing the Network Overhead of Checkpointing in Cycle-harvesting Cluster Environments
Cycle-harvesting systems such as Condor have been developed to make desktop machines in a local area (which are often similar to clusters in hardware configuration) available as ...
Daniel Nurmi, John Brevik, Richard Wolski
PLDI
2005
ACM
14 years 2 months ago
Demystifying on-the-fly spill code
Modulo scheduling is an effective code generation technique that exploits the parallelism in program loops by overlapping iterations. One drawback of this optimization is that reg...
Alex Aletà, Josep M. Codina, Antonio Gonz&a...
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