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139
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CJ
2006
84views more  CJ 2006»
15 years 2 months ago
Instruction Level Parallelism through Microthreading - A Scalable Approach to Chip Multiprocessors
Most microprocessor chips today use an out-of-order instruction execution mechanism. This mechanism allows superscalar processors to extract reasonably high levels of instruction ...
Kostas Bousias, Nabil Hasasneh, Chris R. Jesshope
ISCA
2012
IEEE
260views Hardware» more  ISCA 2012»
13 years 4 months ago
A case for exploiting subarray-level parallelism (SALP) in DRAM
Modern DRAMs have multiple banks to serve multiple memory requests in parallel. However, when two requests go to the same bank, they have to be served serially, exacerbating the h...
Yoongu Kim, Vivek Seshadri, Donghyuk Lee, Jamie Li...
124
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WINE
2009
Springer
178views Economy» more  WINE 2009»
15 years 9 months ago
Computing Optimal Contracts in Series-Parallel Heterogeneous Combinatorial Agencies
We study an economic setting in which a principal motivates a team of strategic agents to exert costly effort toward the success of a joint project. The action taken by each agent...
Yuval Emek, Michal Feldman
FCCM
2006
IEEE
195views VLSI» more  FCCM 2006»
15 years 8 months ago
A Parallel Hardware Architecture for fast Gaussian Elimination over GF(2)
This paper presents a hardware-optimized variant of the well-known Gaussian elimination over GF(2) and its highly efficient implementation. The proposed hardware architecture, we...
Andrey Bogdanov, M. C. Mertens
ICCS
2005
Springer
15 years 8 months ago
Resource-Aware Parallel Adaptive Computation for Clusters
Abstract. Smaller institutions can now maintain local cluster computing environments to support research and teaching in high-performance scientific computation. Researchers can d...
James D. Teresco, Laura Effinger-Dean, Arjun Sharm...