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» Parallelizing time with polynomial circuits
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IPL
2002
90views more  IPL 2002»
13 years 8 months ago
On the approximability of two tree drawing conventions
We consider two aesthetic criteria for the visualization of rooted trees: inclusion and tip-over. Finding the minimum area layout according to either of these two standards is an ...
Paolo Penna
ASAP
2007
IEEE
107views Hardware» more  ASAP 2007»
14 years 3 months ago
A Hardware-Oriented Method for Evaluating Complex Polynomials
A hardware-oriented method for evaluating complex polynomials by solving iteratively a system of linear equations is proposed. Its implementation uses a digit-serial iterations on...
Milos D. Ercegovac, Jean-Michel Muller
GLVLSI
2007
IEEE
171views VLSI» more  GLVLSI 2007»
14 years 3 months ago
Combinational equivalence checking for threshold logic circuits
Threshold logic is gaining prominence as an alternative to Boolean logic. The main reason for this trend is the availability of devices that implement these circuits efficiently (...
Tejaswi Gowda, Sarma B. K. Vrudhula, Goran Konjevo...
TCAD
2002
146views more  TCAD 2002»
13 years 8 months ago
Static scheduling of multidomain circuits for fast functional verification
With the advent of system-on-a-chip design, many application specific integrated circuits (ASICs) now require multiple design clocks that operate asynchronously to each other. This...
Murali Kudlugi, Russell Tessier
ICCAD
2006
IEEE
126views Hardware» more  ICCAD 2006»
14 years 6 months ago
Optimizing yield in global routing
We present the first efficient approach to global routing that takes spacing-dependent costs into account and provably finds a near-optimum solution including these costs. We sh...
Dirk Müller