356 search results - page 24 / 72 » Parallelizing time with polynomial circuits |
JSA
2006
13 years 9 months ago
2006
A NULL Cycle Reduction (NCR) technique is developed to increase the throughput of NULL Convention Logic systems, by reducing the time required to flush complete DATA wavefronts, c...
STOC
2009
ACM
14 years 9 months ago
2009
ACM
The "direct product code" of a function f gives its values on all k-tuples (f(x1), . . . , f(xk)). This basic construct underlies "hardness amplification" in c...
ICCAD
2008
IEEE
14 years 6 months ago
2008
IEEE
Abstract— Power consumption has become a crucial problem in modern circuit design. Multiple Supply Voltage (MSV) design is introduced to provide higher flexibility in controllin...
IPPS
2003
IEEE
14 years 2 months ago
2003
IEEE
With the current trend in integration of more complex systems on chip there is a need for better communication infrastructure on chip that will increase the available bandwidth an...
DAC
1999
ACM
14 years 10 months ago
1999
ACM
The concept of improving the timing behavior of a circuit by relocating registers is called retiming and was first presented by Leiserson and Saxe. They showed that the problem of...