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» Parallelizing time with polynomial circuits
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PADS
2004
ACM
14 years 2 months ago
Exploiting Symmetry for Partitioning Models in Parallel Discrete Event Simulation
We investigated the benefit of exploiting the symmetries of graphs for partitioning. We represent the model to be simulated by a weighted graph. Graph symmetries are studied in th...
Jan Lemeire, Bart Smets, Philippe Cara, Erik F. Di...
CORR
2010
Springer
59views Education» more  CORR 2010»
13 years 7 months ago
Refinement and Verification of Real-Time Systems
This paper discusses highly general mechanisms for specifying the refinement of a real-time system as a collection of lower level parallel components that preserve the timing and ...
Paul Z. Kolano, Carlo A. Furia, Richard A. Kemmere...
ICALP
2009
Springer
14 years 9 months ago
Limits and Applications of Group Algebras for Parameterized Problems
The algebraic framework introduced in [Koutis, Proc. of the 35th ICALP 2008] reduces several combinatorial problems in parameterized complexity to the problem of detecting multili...
Ioannis Koutis, Ryan Williams
ICCAD
2003
IEEE
113views Hardware» more  ICCAD 2003»
14 years 6 months ago
Retiming with Interconnect and Gate Delay
In this paper, we study the problem of retiming of sequential circuits with both interconnect and gate delay. Most retiming algorithms have assumed ideal conditions for the non-lo...
Chris C. N. Chu, Evangeline F. Y. Young, Dennis K....
DATE
2003
IEEE
103views Hardware» more  DATE 2003»
14 years 2 months ago
Reduced Delay Uncertainty in High Performance Clock Distribution Networks
The design of clock distribution networks in synchronous digital systems presents enormous challenges. Controlling the clock signal delay in the presence of various noise sources,...
Dimitrios Velenis, Marios C. Papaefthymiou, Eby G....