356 search results - page 3 / 72 » Parallelizing time with polynomial circuits |
ICPP
1996
IEEE
13 years 11 months ago
1996
IEEE
Data locality and synchronization overhead are two important factors that affect the performance of applications on multiprocessors. Loop fusion is an effective way for reducing s...
GLVLSI
2003
IEEE
14 years 9 days ago
2003
IEEE
This paper first presents an accurate and efficient method of estimating the short circuit energy dissipation and the output transition time of CMOS buffers. Next the paper descri...
DAC
2009
ACM
14 years 8 months ago
2009
ACM
As VLSI technology enters the nanoscale regime, interconnect delay has become the bottleneck of the circuit timing. As one of the most powerful techniques for interconnect optimiz...
FSTTCS
2009
Springer
14 years 1 months ago
2009
Springer
We study the problem of polynomial identity testing (PIT) for depth 2 arithmetic circuits over matrix algebra. We show that identity testing of depth 3 (ΣΠΣ) arithmetic circuit...
CONCUR
1998
Springer
13 years 11 months ago
1998
Springer
Abstract. We summarize and reorganize some of the last decade's research on real-time extensions of temporal logic. Our main focus is on tableau constructions for model checki...