356 search results - page 41 / 72 » Parallelizing time with polynomial circuits |
JCO
2011
13 years 4 months ago
2011
Discrete gate sizing is a critical optimization in VLSI circuit design. Given a set of available gate sizes, discrete gate sizing problem asks to assign a size to each gate such th...
JSC
2010
13 years 7 months ago
2010
We prove two versions of Stickelberger’s Theorem for positive dimensions and use them to compute the connected and irreducible components of a complex algebraic variety. If the ...
ASPDAC
2004
ACM
14 years 2 months ago
2004
ACM
— The problem of minimizing dynamic power consumption by scaling down the supply voltage of computational elements off critical paths is widely addressed in the literature for th...
CSL
2010
Springer
13 years 9 months ago
2010
Springer
We study probabilistic complexity classes and questions of derandomisation from a logical point of view. For each logic L we introduce a new logic BPL, bounded error probabilistic ...
JAIR
1998
13 years 8 months ago
1998
This article studies the problem of modifying the action ordering of a plan in order to optimise the plan according to various criteria. One of these criteria is to make a plan le...