356 search results - page 58 / 72 » Parallelizing time with polynomial circuits |
HPCA
2003
IEEE
14 years 8 months ago
2003
IEEE
With the scaling of technology and the need for higher performance and more functionality, power dissipation is becoming a major bottleneck for microprocessor designs. Pipeline ba...
ISSS
2002
IEEE
14 years 25 days ago
2002
IEEE
We have fabricated a Chip Multiprocessor prototype code-named Merlot to proof our novel speculative multithreading architecture. On Merlot, multiple threads provide wider issue wi...
COORDINATION
2009
Springer
13 years 11 months ago
2009
Springer
Abstract. Reo is a channel-based coordination model whose operational semantics is given by Constraint Automata (CA). Quantitative Constraint Automata extend CA (and hence, Reo) wi...
WSC
1998
13 years 9 months ago
1998
VHDL-AMS is an Analog and Mixed-Signal extension to the Very High Speed Integrated Circuit Hardware Description Language (VHDL). With the standardization of VHDL-AMS, capable and ...
ESA
2007
Springer
13 years 11 months ago
2007
Springer
We consider the price of selfish routing in terms of tradeoffs and from an average-case perspective. Each player in a network game seeks to send a message with a certain length by...