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» Parameterized Complexity Classes under Logical Reductions
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FPGA
2005
ACM
80views FPGA» more  FPGA 2005»
14 years 1 months ago
Simultaneous timing-driven placement and duplication
Logic duplication is an effective method for improving circuit performance. In this paper we present an algorithm named SPD that performs simultaneous placement and duplication to...
Gang Chen, Jason Cong
FUZZIEEE
2007
IEEE
14 years 2 months ago
Optimised Generalised Type-2 Join and Meet Operations
— The inferencing stage of a type-2 fuzzy inferencing system is driven by join and meet operations. As conventionally implemented these algorithms are computationally complex. Th...
Sarah Greenfield, Robert John
ICCAD
2007
IEEE
125views Hardware» more  ICCAD 2007»
14 years 5 months ago
A methodology for timing model characterization for statistical static timing analysis
While the increasing need for addressing process variability in sub-90nm VLSI technologies has sparkled a large body of statistical timing and optimization research, the realizati...
Zhuo Feng, Peng Li
HYBRID
2005
Springer
14 years 1 months ago
Hybrid Decentralized Control of Large Scale Systems
Abstract. Motivated by three applications which are under investigation at the Honeywell Research Laboratory in Minneapolis, we introduce a class of large scale control problems. I...
Francesco Borrelli, Tamás Keviczky, Gary J....
ICCAD
2010
IEEE
156views Hardware» more  ICCAD 2010»
13 years 6 months ago
Boolean matching of function vectors with strengthened learning
Boolean matching for multiple-output functions determines whether two given (in)completely-specified function vectors can be identical to each other under permutation and/or negat...
Chih-Fan Lai, Jie-Hong R. Jiang, Kuo-Hua Wang