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» Parameterized Memory Models and Concurrent Separation Logic
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SBCCI
2003
ACM
213views VLSI» more  SBCCI 2003»
14 years 26 days ago
Algorithms and Tools for Network on Chip Based System Design
Network on Chip (NoC) is a new paradigm for designing core based System on Chips. It supports high degree of reusability and is scalable. In this paper, an efficient Two-Step Gene...
Tang Lei, Shashi Kumar
CONCURRENCY
2002
116views more  CONCURRENCY 2002»
13 years 7 months ago
Parallel implementation of the fluid particle model for simulating complex fluids in the mesoscale
Dissipative particle dynamics (DPD) and its generalization - fluid particle model (FPM) - represent the "fluid particle" approach for simulating fluid-like behavior in t...
Krzysztof Boryczko, Witold Dzwinel, David A. Yuen
ISLPED
2004
ACM
102views Hardware» more  ISLPED 2004»
14 years 1 months ago
Microarchitectural power modeling techniques for deep sub-micron microprocessors
The need to perform early design studies that combine architectural simulation with power estimation has become critical as power has become a design constraint whose importance h...
Nam Sung Kim, Taeho Kgil, Valeria Bertacco, Todd M...
IICAI
2007
13 years 9 months ago
Logics for Action
Logics of action, for reasoning about the effects of state change, and logics of belief, accounting for belief revision and update, have much in common. Furthermore, we may underta...
Michael P. Fourman
CEC
2008
IEEE
14 years 2 months ago
Finding liveness errors with ACO
Abstract— Model Checking is a well-known and fully automatic technique for checking software properties, usually given as temporal logic formulae on the program variables. Most o...
J. Francisco Chicano, Enrique Alba