149 search results - page 24 / 30 » Parametric Fault Simulation and Test Vector Generation |
GECCO
2004
Springer
14 years 22 days ago
2004
Springer
Abstract. The need for effective testing techniques for architectural level descriptions is widely recognised. However, due to the variety of domain-specific architectural descript...
VTS
2007
IEEE
14 years 1 months ago
2007
IEEE
The sensitivity of very deep submicron designs to supply voltage noise is increasing due to higher path delay variations and reduced noise margins with supply noise scaling. The s...
DAC
1997
ACM
13 years 11 months ago
1997
ACM
The biggest obstacle in the formal verification of large designs is their very large state spaces, which cannot be handled even by techniques such as implicit state space travers...
ICT
2004
Springer
14 years 22 days ago
2004
Springer
We propose a new approach to fault detection and diagnosis in third-generation (3G) cellular networks using competitive neural algorithms. For density estimation purposes, a given ...
CONSTRAINTS
2007
13 years 7 months ago
2007
In the ECAD area, the Test Generation (TG) problem consists in finding an input vector test for some possible diagnosis (a set of faults) of a digital circuit. Such tests may have ...