8 search results - page 2 / 2 » Parasitic capacitance modeling for multilevel interconnects |
3DIC
2009
IEEE
14 years 5 months ago
2009
IEEE
Abstract—Modeling parasitic parameters of Through-SiliconVia (TSV) structures is essential in exploring electrical characteristics such as delay and signal integrity (SI) of circ...
ICCAD
2000
IEEE
14 years 3 months ago
2000
IEEE
The increasing size of integrated systems combined with deep submicron physical modeling details creates an explosion in RLC interconnect modeling complexity of unmanageable propo...
CDES
2006
14 years 7 days ago
2006
A neural network approach is presented for modeling and characterization of on-chip copper spiral inductors. The approach involves the creation of neural network models to map 3D ...