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ARITH
2003
IEEE
14 years 3 months ago
High-Performance Left-to-Right Array Multiplier Design
We propose a split array multiplier organized in a left-to-right leapfrog (LRLF) structure with reduced delay compared to conventional array multipliers. Moreover, the proposed de...
Zhijun Huang, Milos D. Ercegovac
PEPM
2011
ACM
13 years 21 days ago
Calculating tree navigation with symmetric relational zipper
Navigating through tree structures is a core operation in tree processing programs. Most notably, XML processing programs intensively use XPath, the path specification language t...
Yuta Ikeda, Susumu Nishimura
ATVA
2007
Springer
115views Hardware» more  ATVA 2007»
14 years 4 months ago
A Compositional Semantics for Dynamic Fault Trees in Terms of Interactive Markov Chains
Abstract. Dynamic fault trees (DFTs) are a versatile and common formalism to model and analyze the reliability of computer-based systems. This paper presents a formal semantics of ...
Hichem Boudali, Pepijn Crouzen, Mariëlle Stoe...
ICALP
2011
Springer
13 years 1 months ago
On Tree-Constrained Matchings and Generalizations
We consider the following Tree-Constrained Bipartite Matching problem: Given two rooted trees T1 = (V1, E1), T2 = (V2, E2) and a weight function w : V1 × V2 → R+, find a maximu...
Stefan Canzar, Khaled M. Elbassioni, Gunnar W. Kla...
ISPD
2003
ACM
133views Hardware» more  ISPD 2003»
14 years 3 months ago
Optimal minimum-delay/area zero-skew clock tree wire-sizing in pseudo-polynomial time
In 21st-Century VLSI design, clocking plays crucial roles for both performance and timing convergence. Due to their non-convex nature, optimal minimum-delay/area zero-skew wire-si...
Jeng-Liang Tsai, Tsung-Hao Chen, Charlie Chung-Pin...