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ACSD
1998
IEEE
121views Hardware» more  ACSD 1998»
13 years 12 months ago
Identifying State Coding Conflicts in Asynchronous System Specifications Using Petri Net Unfoldings
State coding conflict detection is a fundamental part of synthesis of asynchronous concurrent systems from their specifications as Signal Transition Graphs (STGs), which are a spe...
Alex Kondratyev, Jordi Cortadella, Michael Kishine...
AUTOMATICA
2011
13 years 2 months ago
Sequential linear quadratic control of bilinear parabolic PDEs based on POD model reduction
We present a framework to solve a finite-time optimal control problem for parabolic partial differential equations (PDEs) with diffusivity-interior actuators, which is motivate...
Chao Xu, Yongsheng Ou, Eugenio Schuster
ISPD
2003
ACM
110views Hardware» more  ISPD 2003»
14 years 27 days ago
Explicit gate delay model for timing evaluation
Delay evaluation is always a crucial concern in the VLSI design and it becomes increasingly more critical in the nowadays deep-submicron technology. To obtain an accurate delay va...
Muzhou Shao, Martin D. F. Wong, Huijing Cao, Youxi...
DATE
2010
IEEE
171views Hardware» more  DATE 2010»
14 years 22 days ago
Statistical static timing analysis using Markov chain Monte Carlo
—We present a new technique for statistical static timing analysis (SSTA) based on Markov chain Monte Carlo (MCMC), that allows fast and accurate estimation of the right-hand tai...
Yashodhan Kanoria, Subhasish Mitra, Andrea Montana...
ASYNC
2001
IEEE
136views Hardware» more  ASYNC 2001»
13 years 11 months ago
Efficient Exact Two-Level Hazard-Free Logic Minimization
This paper presents a new approach to two-level hazardfree sum-of-products logic minimization. No currently available minimizers for single-output literal-exact two-level hazard-f...
Chris J. Myers, Hans M. Jacobson