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» Participatory Design: Issues and Concerns
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ICCD
2004
IEEE
119views Hardware» more  ICCD 2004»
14 years 4 months ago
Simultaneous Scheduling, Binding and Layer Assignment for Synthesis of Vertically Integrated 3D Systems
Three dimensional vertically integrated systems allow active devices to be placed on multiple device layers. In recent years, a number of research efforts have addressed physical ...
Madhubanti Mukherjee, Ranga Vemuri
ISCA
2007
IEEE
192views Hardware» more  ISCA 2007»
14 years 1 months ago
Analysis of redundancy and application balance in the SPEC CPU2006 benchmark suite
The recently released SPEC CPU2006 benchmark suite is expected to be used by computer designers and computer architecture researchers for pre-silicon early design analysis. Partia...
Aashish Phansalkar, Ajay Joshi, Lizy Kurian John
GLVLSI
2003
IEEE
173views VLSI» more  GLVLSI 2003»
14 years 20 days ago
40 MHz 0.25 um CMOS embedded 1T bit-line decoupled DRAM FIFO for mixed-signal applications
An embedded 40 MHz FIFO buffer for use in mixed-signal information processing applications is presented. The buffer design uses a 1T DRAM topology for its unit memory cell compone...
Michael I. Fuller, James P. Mabry, John A. Hossack...
ACMDIS
2010
ACM
13 years 7 months ago
Some consideration on the (in)effectiveness of residential energy feedback systems
Energy feedback systems, particularly residential energy feedback systems (REFS), have emerged as a key area for HCI and interaction design. However, we argue that HCI researchers...
James Pierce, Chloe Fan, Derek Lomas, Gabriela Mar...
ISCA
2012
IEEE
333views Hardware» more  ISCA 2012»
11 years 9 months ago
Reducing memory reference energy with opportunistic virtual caching
Most modern cores perform a highly-associative translation look aside buffer (TLB) lookup on every memory access. These designs often hide the TLB lookup latency by overlapping it...
Arkaprava Basu, Mark D. Hill, Michael M. Swift