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SIGSOFT
2007
ACM
14 years 8 months ago
Quantitative verification: models techniques and tools
Automated verification is a technique for establishing if certain properties, usually expressed in temporal logic, hold for a system model. The model can be defined using a high-l...
Marta Z. Kwiatkowska
SIGSOFT
2007
ACM
14 years 8 months ago
Finding bugs efficiently with a SAT solver
We present an approach for checking code against rich specifications, based on existing work that consists of encoding the program in a relational logic and using a constraint sol...
Julian Dolby, Mandana Vaziri, Frank Tip
ICDT
2009
ACM
175views Database» more  ICDT 2009»
14 years 8 months ago
Structural characterizations of schema-mapping languages
Schema mappings are declarative specifications that describe the relationship between two database schemas. In recent years, there has been an extensive study of schema mappings a...
Balder ten Cate, Phokion G. Kolaitis
VLSID
2006
IEEE
129views VLSI» more  VLSID 2006»
14 years 8 months ago
A Stimulus-Free Probabilistic Model for Single-Event-Upset Sensitivity
With device size shrinking and fast rising frequency ranges, effect of cosmic radiations and alpha particles known as Single-Event-Upset (SEU), Single-Eventtransients (SET), is a ...
Mohammad Gh. Mohammad, Laila Terkawi, Muna Albasma...
POPL
2005
ACM
14 years 8 months ago
Enterprise privacy promises and enforcement
Several formal languages have been proposed to encode privacy policies, ranging from the Platform for Privacy Preferences (P3P), intended for communicating privacy policies to con...
Adam Barth, John C. Mitchell