338 search results - page 4 / 68 » Partitioning of VLSI Circuits and Systems |
145
click to vote
VLSID
2002
IEEE
16 years 4 months ago
2002
IEEE
IDDQ testing has been used as a test technique to supplement voltage testing of CMOS chips. The idea behind IDDQ testing is to declare a chip as faulty if the steady-state current...
120
click to vote
ICES
2000
Springer
15 years 8 months ago
2000
Springer
A new system for research on hardware evolution of analog VLSI circuits is proposed. The heart of the system is a CMOS chip providing an array of 16
198
click to vote
TIM
2010
14 years 11 months ago
2010
In this paper, a novel low-power design technique is proposed to minimize the standby leakage power in nanoscale CMOS very large scale integration (VLSI) systems by generating the ...
143
click to vote
DFT
2008
IEEE
15 years 11 months ago
2008
IEEE
The paper presents a new technique for designing a concurrently checking combinational circuit. The technique is based on partitioning the circuit into two independent sub-circuit...
131
click to vote
IJON
2006
15 years 4 months ago
2006
: In this paper we present a complete neuromorphic image processing system and we report the development of an integrated CMOS low-power circuit to test the feasibility of its diff...