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» Patching Processor Design Errors
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CVPR
2008
IEEE
14 years 10 months ago
Regression from patch-kernel
In this paper, we present a patch-based regression framework for addressing the human age and head pose estimation problems. Firstly, each image is encoded as an ensemble of order...
Shuicheng Yan, Xi Zhou, Ming Liu, Mark Hasegawa-Jo...
IPPS
2006
IEEE
14 years 2 months ago
Broadcasting and routing in faulty mesh networks
— Broadcasting is a data communication task in which one processor sends the same message to all other processors. Routing is a task where a source processor sends a message to a...
Milos Stojmenovic, Amiya Nayak
MICRO
2003
IEEE
166views Hardware» more  MICRO 2003»
14 years 1 months ago
Razor: A Low-Power Pipeline Based on Circuit-Level Timing Speculation
With increasing clock frequencies and silicon integration, power aware computing has become a critical concern in the design of embedded processors and systems-on-chip. One of the...
Dan Ernst, Nam Sung Kim, Shidhartha Das, Sanjay Pa...
VLSID
2008
IEEE
128views VLSI» more  VLSID 2008»
14 years 9 months ago
Addressing the Challenges of Synchronization/Communication and Debugging Support in Hardware/Software Cosimulation
With increasing adoption of Electronic System Level (ESL) tools, effective design and validation time has reduced to a considerable extent. Cosimulation is found to be a principal...
Banit Agrawal, Timothy Sherwood, Chulho Shin, Simo...
ANSS
2002
IEEE
14 years 1 months ago
Statistical Simulation of Symmetric Multiprocessor Systems
Statistical simulation is driven by a stream of randomly generated instructions, based on statistics collected during a single detailed simulation. This method can give accurate p...
Sébastien Nussbaum, James E. Smith