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» Patching Processor Design Errors
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CAL
2006
13 years 8 months ago
Performance modeling using Monte Carlo simulation
Abstract-- Cycle accurate simulation has long been the primary tool for micro-architecture design and evaluation. Though accurate, the slow speed often imposes constraints on the e...
Ram Srinivasan, Jeanine Cook, Olaf M. Lubeck
ASAP
2008
IEEE
142views Hardware» more  ASAP 2008»
14 years 3 months ago
Managing multi-core soft-error reliability through utility-driven cross domain optimization
As semiconductor processing technology continues to scale down, managing reliability becomes an increasingly difficult challenge in high-performance microprocessor design. Transie...
Wangyuan Zhang, Tao Li
DSN
2006
IEEE
14 years 2 months ago
In-Register Duplication: Exploiting Narrow-Width Value for Improving Register File Reliability
Protecting the register value and its data buses is crucial to reliable computing in high-performance microprocessors due to the increasing susceptibility of CMOS circuitry to sof...
Jie Hu, Shuai Wang, Sotirios G. Ziavras
SP
2002
IEEE
109views Security Privacy» more  SP 2002»
13 years 8 months ago
Scalable atomistic simulation algorithms for materials research
A suite of scalable atomistic simulation programs has been developed for materials research based on space-time multiresolution algorithms. Design and analysis of parallel algorit...
Aiichiro Nakano, Rajiv K. Kalia, Priya Vashishta, ...
IEEEPACT
2008
IEEE
14 years 3 months ago
Skewed redundancy
Technology scaling in integrated circuits has consistently provided dramatic performance improvements in modern microprocessors. However, increasing device counts and decreasing o...
Gordon B. Bell, Mikko H. Lipasti