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» Patching Processor Design Errors
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EUROSYS
2008
ACM
14 years 5 months ago
Documenting and automating collateral evolutions in linux device drivers
The internal libraries of Linux are evolving rapidly, to address new requirements and improve performance. These evolutions, however, entail a massive problem of collateral evolut...
Yoann Padioleau, Julia L. Lawall, René Rydh...
IEEEPACT
2007
IEEE
14 years 2 months ago
Error Detection Using Dynamic Dataflow Verification
Continued scaling of CMOS technology to smaller transistor sizes makes modern processors more susceptible to both transient and permanent hardware faults. Circuitlevel techniques ...
Albert Meixner, Daniel J. Sorin
DSN
2007
IEEE
14 years 3 months ago
Superscalar Processor Performance Enhancement through Reliable Dynamic Clock Frequency Tuning
Synchronous circuits are typically clocked considering worst case timing paths so that timing errors are avoided under all circumstances. In the case of a pipelined processor, thi...
Viswanathan Subramanian, Mikel Bezdek, Naga Durga ...
HPCA
2009
IEEE
14 years 9 months ago
Blueshift: Designing processors for timing speculation from the ground up
Several recent processor designs have proposed to enhance performance by increasing the clock frequency to the point where timing faults occur, and by adding error-correcting supp...
Brian Greskamp, Lu Wan, Ulya R. Karpuzcu, Jeffrey ...
ISCA
2008
IEEE
132views Hardware» more  ISCA 2008»
14 years 3 months ago
Online Estimation of Architectural Vulnerability Factor for Soft Errors
As CMOS technology scales and more transistors are packed on to the same chip, soft error reliability has become an increasingly important design issue for processors. Prior resea...
Xiaodong Li, Sarita V. Adve, Pradip Bose, Jude A. ...