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FPL
2006
Springer
96views Hardware» more  FPL 2006»
13 years 11 months ago
Reducing the Space Complexity of Pipelined Routing Using Modified Range Encoding
Interconnect delays are becoming an increasingly significant part of the critical path delay for circuits implemented in FPGAs. Pipelined interconnects have been proposed to addre...
Allan Carroll, Carl Ebeling
CONEXT
2009
ACM
13 years 8 months ago
Improving internet-wide routing protocols convergence with MRPC timers
The behavior of routing protocols during convergence is critical as it impacts end-to-end performance. Network convergence is particularly important in BGP, the current interdomai...
Anthony J. Lambert, Marc-Olivier Buob, Steve Uhlig
GLOBECOM
2010
IEEE
13 years 5 months ago
Energy-Efficient Power Loading for a MIMO-SVD System and Its Performance in Flat Fading
In this paper we formulate a power loading problem for the spatial subchannels (parallel channels) of a single-carrier MIMO-SVD system. The power loading solution is designed to mi...
Raghavendra S. Prabhu, Babak Daneshrad
CCGRID
2008
IEEE
14 years 1 months ago
Joint Communication and Computation Task Scheduling in Grids
In this paper we present a multicost algorithm for the joint time scheduling of the communication and computation resources that will be used by a task. The proposed algorithm sel...
Kostas Christodoulopoulos, Nikolaos D. Doulamis, E...
DATE
2006
IEEE
91views Hardware» more  DATE 2006»
13 years 11 months ago
Efficient incremental clock latency scheduling for large circuits
The clock latency scheduling problem is usually solved on the sequential graph, also called register-to-register graph. In practice, the the extraction of the sequential graph for...
Christoph Albrecht