Interconnect delays are becoming an increasingly significant part of the critical path delay for circuits implemented in FPGAs. Pipelined interconnects have been proposed to addre...
The behavior of routing protocols during convergence is critical as it impacts end-to-end performance. Network convergence is particularly important in BGP, the current interdomai...
Anthony J. Lambert, Marc-Olivier Buob, Steve Uhlig
In this paper we formulate a power loading problem for the spatial subchannels (parallel channels) of a single-carrier MIMO-SVD system. The power loading solution is designed to mi...
In this paper we present a multicost algorithm for the joint time scheduling of the communication and computation resources that will be used by a task. The proposed algorithm sel...
Kostas Christodoulopoulos, Nikolaos D. Doulamis, E...
The clock latency scheduling problem is usually solved on the sequential graph, also called register-to-register graph. In practice, the the extraction of the sequential graph for...