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ISQED
2002
IEEE
83views Hardware» more  ISQED 2002»
15 years 7 months ago
A Hybrid BIST Architecture and Its Optimization for SoC Testing
This paper presents a hybrid BIST architecture and methods for optimizing it to test systems-on-chip in a cost effective way. The proposed self-test architecture can be implemente...
Gert Jervan, Zebo Peng, Raimund Ubar, Helena Kruus
95
Voted
ITC
1998
IEEE
73views Hardware» more  ITC 1998»
15 years 6 months ago
Maximization of power dissipation under random excitation for burn-in testing
This work proposes an approach to generate weighted random patterns which can maximally excite a circuit during its burn-in testing. The approach is based on a probability model a...
Kuo-Chan Huang, Chung-Len Lee, Jwu E. Chen
CVPR
2007
IEEE
15 years 9 months ago
Learning Generative Models via Discriminative Approaches
Generative model learning is one of the key problems in machine learning and computer vision. Currently the use of generative models is limited due to the difficulty in effective...
Zhuowen Tu
239
Voted
ASUNAM
2011
IEEE
14 years 2 months ago
MultiAspectForensics: Pattern Mining on Large-Scale Heterogeneous Networks with Tensor Analysis
—Modern applications such as web knowledge base, network traffic monitoring and online social networks have made available an unprecedented amount of network data with rich type...
Koji Maruhashi, Fan Guo, Christos Faloutsos
CIARP
2006
Springer
15 years 6 months ago
Feature Selection Based on Mutual Correlation
Feature selection is a critical procedure in many pattern recognition applications. There are two distinct mechanisms for feature selection namely the wrapper methods and the filte...
Michal Haindl, Petr Somol, Dimitrios Ververidis, C...