57 search results - page 5 / 12 » Peak Power Minimization Through Datapath Scheduling |
CLUSTER
2007
IEEE
14 years 4 months ago
2007
IEEE
— The thermal environment of data centers plays a significant role in affecting the energy efficiency and the reliability of data center operation. A dominant problem associate...
TSP
2008
13 years 9 months ago
2008
The focus of this paper is on VLIW instruction scheduling that minimizes the variation of power consumed by the processor during the execution of a target program. We use rough set...
DATE
2008
IEEE
14 years 4 months ago
2008
IEEE
—Increasing integrated circuit (IC) power densities and temperatures may hamper multiprocessor system-on-chip (MPSoC) use in hard real-time systems. This article formalizes the t...
ISVLSI
2005
IEEE
14 years 3 months ago
2005
IEEE
— Direct tunneling current is the major component of static power dissipation of a CMOS circuit for technology below 65nm, where the gate dielectric (SiO2) is very low. We intuit...
DATE
2003
IEEE
14 years 3 months ago
2003
IEEE
We present a high-level synthesis algorithm solving the combined scheduling, allocation and binding problem minimizing area under both latency and maximum power per clock-cycle co...