Reducing the power consumption of computing devices has gained a lot of attention recently. Many research works have focused on reducing power consumption in the off-chip buses as...
Dinesh C. Suresh, Banit Agrawal, Jun Yang 0002, Wa...
This paper presents a compiler technique that reduces the energy consumption of the memory subsystem, for an off-chip partitioned memory architecture having multiple memory banks ...
In this work, we consider low power, wearable pulse oximeter sensors for ambulatory, remote vital signs monitoring applications. It is extremely important for such sensors to main...
Pawan K. Baheti, Harinath Garudadri, Somdeb Majumd...
— We consider the design of optimal strategies for joint power adaptation, rate adaptation and scheduling in a multi-hop wireless network. Most existing strategies control either...
The memory hierarchy of a system can consume up to 50% of microprocessor system power. Previous work has shown that tuning a configurable cache to a particular application can red...