Sciweavers

90 search results - page 11 / 18
» Performance Analysis of Cell Broadband Engine for High Memor...
Sort
View
FCCM
2009
IEEE
115views VLSI» more  FCCM 2009»
14 years 13 days ago
Multi-Core Architecture on FPGA for Large Dictionary String Matching
FPGA has long been considered an attractive platform for high performance implementations of string matching. However, as the size of pattern dictionaries continues to grow, such ...
Qingbo Wang, Viktor K. Prasanna
CODES
2007
IEEE
14 years 2 months ago
Predator: a predictable SDRAM memory controller
Memory requirements of intellectual property components (IP) in contemporary multi-processor systems-on-chip are increasing. Large high-speed external memories, such as DDR2 SDRAM...
Benny Akesson, Kees Goossens, Markus Ringhofer
ERSA
2006
111views Hardware» more  ERSA 2006»
13 years 10 months ago
Promises and Pitfalls of Reconfigurable Supercomputing
Reconfigurable supercomputing (RSC) combines programmable logic chips with high performance microprocessors, all communicating over a high bandwidth, low latency interconnection n...
Maya Gokhale, Christopher Rickett, Justin L. Tripp...
HPCA
2011
IEEE
13 years 9 days ago
Essential roles of exploiting internal parallelism of flash memory based solid state drives in high-speed data processing
Flash memory based solid state drives (SSDs) have shown a great potential to change storage infrastructure fundamentally through their high performance and low power. Most recent ...
Feng Chen, Rubao Lee, Xiaodong Zhang
EUROPAR
2009
Springer
13 years 6 months ago
A Parallel Point Matching Algorithm for Landmark Based Image Registration Using Multicore Platform
Abstract. Point matching is crucial for many computer vision applications. Establishing the correspondence between a large number of data points is a computationally intensive proc...
Lin Yang, Leiguang Gong, Hong Zhang, John L. Noshe...