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TPDS
2002
105views more  TPDS 2002»
15 years 4 months ago
HiPER: A Compact Narrow Channel Router with Hop-by-Hop Error Correction
Multiprocessor architectures demand efficient interprocessor communication to maximize system utilization and performance. To meet future demands, these interconnects must communic...
Phil May, Santithorn Bunchua, D. Scott Wills
158
Voted
ICC
2007
IEEE
130views Communications» more  ICC 2007»
15 years 11 months ago
Queuing with Adaptive Modulation over MIMO Wireless Links for Deadline Constrained Traffic: Cross-Layer Analysis and Design
In this paper, we consider a deadline constrained traffic and analyze the joint effects of packet queuing and adaptive modulation (AM) for packet transmission in MIMO systems. We p...
Jalil S. Harsini, Farshad Lahouti
FROCOS
2007
Springer
15 years 10 months ago
Architecting Solvers for SAT Modulo Theories: Nelson-Oppen with DPLL
We offer a transition system representing a high-level but detailed architecture for SMT solvers that combine a propositional SAT engine with solvers for multiple disjoint theorie...
Sava Krstic, Amit Goel
MONET
2008
150views more  MONET 2008»
15 years 4 months ago
A Multi-radio 802.11 Mesh Network Architecture
Routers equipped with multiple 802.11 radios can alleviate capacity problems in wireless mesh networks. However, a practical, complete system architecture that can realize the bene...
Krishna N. Ramachandran, Irfan Sheriff, Elizabeth ...
DAC
2003
ACM
16 years 5 months ago
Accurate timing analysis by modeling caches, speculation and their interaction
Schedulability analysis of real-time embedded systems requires worst case timing guarantees of embedded software performance. This involves not only language level program analysi...
Xianfeng Li, Tulika Mitra, Abhik Roychoudhury