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IPPS
2005
IEEE
14 years 1 months ago
Runtime Empirical Selection of Loop Schedulers on Hyperthreaded SMPs
Hyperthreaded (HT) and simultaneous multithreaded (SMT) processors are now available in commodity workstations and servers. This technology is designed to increase throughput by e...
Yun Zhang, Michael Voss
PATMOS
2004
Springer
14 years 1 months ago
Application Analysis with Integrated Identification of Complex Instructions for Configurable Processors
Abstract. An extensible and configurable processor is a programmable platform offering the possibility to customize the instruction set and/or underlying microarchitecture. Efficie...
Nikolaos Kavvadias, Spiridon Nikolaidis
IEEEPACT
2008
IEEE
14 years 2 months ago
Meeting points: using thread criticality to adapt multicore hardware to parallel regions
We present a novel mechanism, called meeting point thread characterization, to dynamically detect critical threads in a parallel region. We define the critical thread the one with...
Qiong Cai, José González, Ryan Rakvi...
OOPSLA
2010
Springer
13 years 6 months ago
Hera-JVM: a runtime system for heterogeneous multi-core architectures
Heterogeneous multi-core processors, such as the IBM Cell processor, can deliver high performance. However, these processors are notoriously difficult to program: different cores...
Ross McIlroy, Joe Sventek
IISWC
2006
IEEE
14 years 1 months ago
Performance Characterization of SPEC CPU2006 Integer Benchmarks on x86-64 Architecture
— As x86-64 processors become the CPU of choice for the personal computer market, it becomes increasingly important to understand the performance we can expect by migrating appli...
Dong Ye, Joydeep Ray, Christophe Harle, David R. K...