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ISCA
2011
IEEE
313views Hardware» more  ISCA 2011»
13 years 9 days ago
FabScalar: composing synthesizable RTL designs of arbitrary cores within a canonical superscalar template
A growing body of work has compiled a strong case for the single-ISA heterogeneous multi-core paradigm. A single-ISA heterogeneous multi-core provides multiple, differently-design...
Niket Kumar Choudhary, Salil V. Wadhavkar, Tanmay ...
ML
2007
ACM
156views Machine Learning» more  ML 2007»
13 years 8 months ago
Active learning for logistic regression: an evaluation
Which active learning methods can we expect to yield good performance in learning binary and multi-category logistic regression classifiers? Addressing this question is a natural ...
Andrew I. Schein, Lyle H. Ungar
PERCOM
2005
ACM
14 years 8 months ago
When Does Opportunistic Routing Make Sense?
Different opportunistic routing protocols have been proposed recently for routing in sensor networks. These protocols exploit the redundancy among nodes by using a node that is av...
Adam Wolisz, Jan M. Rabaey, Rahul C. Shah, Sven Wi...
ML
2011
ACM
308views Machine Learning» more  ML 2011»
13 years 3 months ago
Relational information gain
Abstract. Type Extension Trees (TET) have been recently introduced as an expressive representation language allowing to encode complex combinatorial features of relational entities...
Marco Lippi, Manfred Jaeger, Paolo Frasconi, Andre...
MICRO
2005
IEEE
130views Hardware» more  MICRO 2005»
14 years 2 months ago
Exploiting Vector Parallelism in Software Pipelined Loops
An emerging trend in processor design is the addition of short vector instructions to general-purpose and embedded ISAs. Frequently, these extensions are employed using traditiona...
Samuel Larsen, Rodric M. Rabbah, Saman P. Amarasin...