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DATE
2005
IEEE
116views Hardware» more  DATE 2005»
14 years 2 months ago
A Complete Network-On-Chip Emulation Framework
Current Systems-On-Chip (SoC) execute applications that demand extensive parallel processing. Networks-OnChip (NoC) provide a structured way of realizing interconnections on silic...
Nicolas Genko, David Atienza, Giovanni De Micheli,...
ITNG
2010
IEEE
14 years 2 months ago
Accurate Assessment of Link Loss Rate in Wireless Mesh Networks
A number of routing metrics have been proposed to select a path with better performance in wireless mesh networks. Most of them partially rely on link loss rates when evaluating t...
Bing Qi, Saad Biaz, Fangyang Shen
ISVLSI
2008
IEEE
143views VLSI» more  ISVLSI 2008»
14 years 3 months ago
BTB Access Filtering: A Low Energy and High Performance Design
Powerful branch predictors along with a large branch target buffer (BTB) are employed in superscalar processors for instruction-level parallelism exploitation. However, the large ...
Shuai Wang, Jie Hu, Sotirios G. Ziavras
CLUSTER
2007
IEEE
14 years 3 months ago
Balancing productivity and performance on the cell broadband engine
— The Cell Broadband Engine (BE) is a heterogeneous multicore processor, combining a general-purpose POWER architecture core with eight independent single-instructionmultiple-dat...
Sadaf R. Alam, Jeremy S. Meredith, Jeffrey S. Vett...
ISPASS
2009
IEEE
14 years 4 months ago
Machine learning based online performance prediction for runtime parallelization and task scheduling
—With the emerging many-core paradigm, parallel programming must extend beyond its traditional realm of scientific applications. Converting existing sequential applications as w...
Jiangtian Li, Xiaosong Ma, Karan Singh, Martin Sch...