472 search results - page 18 / 95 » Performance Evaluation of Memory Caches in Multiprocessors |
IPPS
2000
IEEE
13 years 12 months ago
2000
IEEE
Parallel programs that modify shared data in a cachecoherent multiprocessor with a write-invalidate coherence protocol create ownership overhead in the form of ownership acquisiti...
IPPS
2005
IEEE
14 years 1 months ago
2005
IEEE
With the latest high-end computing nodes combining shared-memory multiprocessing with hardware multithreading, new scheduling policies are necessary for workloads consisting of mu...
WSC
1997
13 years 8 months ago
1997
We present an extension to an existing SPARC V8 instruction set simulator, SimICS, to support accurate profiling of branches and instruction cache misses. SimICS had previously su...
DATE
2006
IEEE
13 years 11 months ago
2006
IEEE
In current multi-media systems major parts of the functionality consist of software tasks executed on a set of concurrently operating processors. Those tasks interfere with each o...
TC
2010
13 years 5 months ago
2010
—The number of CPUs in chip multiprocessors is growing at the Moore’s Law rate, due to continued technology advances. However, new technologies pose serious reliability challen...