472 search results - page 27 / 95 » Performance Evaluation of Memory Caches in Multiprocessors |
ISCA
2006
IEEE
14 years 1 months ago
2006
IEEE
Prior research indicates that there is much spatial variation in applications' memory access patterns. Modern memory systems, however, use small fixed-size cache blocks and a...
ISCA
2011
IEEE
2011
IEEE
Increasing the effectiveness of directory caches by deactivating coherence for private memory blocks
12 years 11 months ago
To meet the demand for more powerful high-performance shared-memory servers, multiprocessor systems must incorporate efficient and scalable cache coherence protocols, such as thos...
IPPS
1992
IEEE
13 years 11 months ago
1992
IEEE
This paper presents a hybrid shared memory architecture which combines the scalability of a multistage interconnection network with the contention reduction benefits of coherent c...
ISCA
1994
IEEE
13 years 11 months ago
1994
IEEE
Today's commodity microprocessors require a low latency memory system to achieve high sustained performance. The conventional high-performance memory system provides fast dat...
DSN
2011
IEEE
12 years 7 months ago
2011
IEEE
—Aggressive technology scaling causes chip multiprocessors increasingly error-prone. Core-level faulttolerant approaches bind two cores to implement redundant execution and error...