472 search results - page 44 / 95 » Performance Evaluation of Memory Caches in Multiprocessors |
CGO
2006
IEEE
14 years 2 months ago
2006
IEEE
Software code caches are increasingly being used to amortize the runtime overhead of dynamic optimizers, simulators, emulators, dynamic translators, dynamic compilers, and other t...
HPCA
2001
IEEE
14 years 9 months ago
2001
IEEE
The memory overhead introduced by directories constitutes a major hurdle in the scalability of cc-NUMA architectures, which makes the shared-memory paradigm unfeasible for very la...
ICS
1999
Tsinghua U.
14 years 1 months ago
1999
Tsinghua U.
Hydra is a chip multiprocessor (CMP) with integrated support for thread-level speculation. Thread-level speculation provides a way to parallelize sequential programs without the n...
VLDB
1999
ACM
14 years 1 months ago
1999
ACM
As random access memory gets cheaper, it becomes increasingly affordable to build computers with large main memories. We consider decision support workloads within the context of...
ISCA
2003
IEEE
14 years 2 months ago
2003
IEEE
Trends in microprocessors of increasing die size and clock speed and decreasing feature sizes have fueled rapidly increasing performance. However, the limited improvements in DRAM...