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» Performance Evaluation of Memory Caches in Multiprocessors
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ICDCS
2007
IEEE
14 years 3 months ago
STEP: Sequentiality and Thrashing Detection Based Prefetching to Improve Performance of Networked Storage Servers
State-of-the-art networked storage servers are equipped with increasingly powerful computing capability and large DRAM memory as storage caches. However, their contribution to the...
Shuang Liang, Song Jiang, Xiaodong Zhang
DSD
2008
IEEE
139views Hardware» more  DSD 2008»
13 years 10 months ago
Revisiting the Cache Effect on Multicore Multithreaded Network Processors
Caching mechanism has achieved great success in general purpose processor; however, its deployment in Network Processor (NP) raises questions over its effectiveness under the new ...
Zhen Liu, Jia Yu, Xiaojun Wang, Bin Liu, Laxmi N. ...
HPCA
2009
IEEE
14 years 9 months ago
A novel architecture of the 3D stacked MRAM L2 cache for CMPs
Magnetic Random Access Memory (MRAM) is considered to be a promising future memory technology due to its low leakage power, high density and fast read speed. The heterogeneous int...
Guangyu Sun, Xiangyu Dong, Yuan Xie, Jian Li, Yira...
WSC
1997
13 years 10 months ago
A Hybrid Tool for the Performance Evaluation of NUMA Architectures
We present a system for describing and solving closed queuing network models of the memory access performance of NUMA architectures. The system consists of a model description lan...
James Westall, Robert Geist
HPCA
2002
IEEE
14 years 9 months ago
Exploiting Choice in Resizable Cache Design to Optimize Deep-Submicron Processor Energy-Delay
Cache memories account for a significant fraction of a chip's overall energy dissipation. Recent research advocates using "resizable" caches to exploit cache requir...
Se-Hyun Yang, Michael D. Powell, Babak Falsafi, T....