472 search results - page 72 / 95 » Performance Evaluation of Memory Caches in Multiprocessors |
EUROPAR
2008
Springer
13 years 10 months ago
2008
Springer
Chip multiprocessors designed for streaming applications such as Cell BE offer impressive peak performance but suffer from limited bandwidth to offchip main memory. As the number o...
HPCA
2007
IEEE
14 years 9 months ago
2007
IEEE
Transactional Memory (TM) provides mechanisms that promise to simplify parallel programming by eliminating the need for locks and their associated problems (deadlock, livelock, pr...
CASES
2010
ACM
13 years 6 months ago
2010
ACM
We present a fine-grain dynamic instruction placement algorithm for small L0 scratch-pad memories (spms), whose unit of transfer can be an individual instruction. Our algorithm ca...
MICRO
2010
IEEE
13 years 6 months ago
2010
IEEE
Advanced Synchronization Facility (ASF) is an AMD64 hardware extension for lock-free data structures and transactional memory. It provides a speculative region that atomically exec...
IPPS
1998
IEEE
14 years 29 days ago
1998
IEEE
Abstract. The nano-threads programming model was proposed to effectively integrate multiprogramming on shared-memory multiprocessors, with the exploitation of fine-grain parallelis...