Sciweavers

64 search results - page 11 / 13
» Performance Evaluation of Router Switching Fabrics
Sort
View
RTAS
2007
IEEE
14 years 1 months ago
Full Duplex Switched Ethernet for Next Generation "1553B"-Based Applications
Over the last thirty years, the MIL-STD 1553B data bus has been used in many embedded systems, like aircrafts, ships, missiles and satellites. However, the increasing number and c...
Ahlem Mifdaoui, Fabrice Frances, Christian Fraboul
WSC
2007
13 years 9 months ago
Modeling the performance of low latency queueing for emergency telecommunications
Event simulation and analytic modeling are used to evaluate the performance of Low Latency Queueing (LLQ), a queueing discipline available in some Internet packet switching router...
Denise M. Bevilacqua Masi, Martin J. Fischer, Davi...
MICRO
2010
IEEE
130views Hardware» more  MICRO 2010»
13 years 5 months ago
Pseudo-Circuit: Accelerating Communication for On-Chip Interconnection Networks
As the number of cores on a single chip increases with more recent technologies, a packet-switched on-chip interconnection network has become a de facto communication paradigm for ...
Minseon Ahn, Eun Jung Kim
PDP
2010
IEEE
14 years 2 months ago
Impact of Parallel Workloads on NoC Architecture Design
— Due to the multi-core processors, the importance of parallel workloads has increased considerably. However, manycore chips demand new interconnection strategies, since traditio...
Henrique Cota de Freitas, Lucas Mello Schnorr, Mar...
HPCA
2009
IEEE
14 years 8 months ago
Design and evaluation of a hierarchical on-chip interconnect for next-generation CMPs
Performance and power consumption of an on-chip interconnect that forms the backbone of Chip Multiprocessors (CMPs), are directly influenced by the underlying network topology. Bo...
Reetuparna Das, Soumya Eachempati, Asit K. Mishra,...