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EUROSYS
2010
ACM
14 years 5 months ago
A Comprehensive Scheduler for Asymmetric Multicore Systems
Symmetric-ISA (instruction set architecture) asymmetricperformance multicore processors were shown to deliver higher performance per watt and area for codes with diverse architect...
Juan Carlos Saez, Manuel Prieto Matias, Alexandra ...
ICS
2009
Tsinghua U.
14 years 2 months ago
Less reused filter: improving l2 cache performance via filtering less reused lines
The L2 cache is commonly managed using LRU policy. For workloads that have a working set larger than L2 cache, LRU behaves poorly, resulting in a great number of less reused lines...
Lingxiang Xiang, Tianzhou Chen, Qingsong Shi, Wei ...
FPGA
2010
ACM
232views FPGA» more  FPGA 2010»
13 years 8 months ago
High-throughput bayesian computing machine with reconfigurable hardware
We use reconfigurable hardware to construct a high throughput Bayesian computing machine (BCM) capable of evaluating probabilistic networks with arbitrary DAG (directed acyclic gr...
Mingjie Lin, Ilia Lebedev, John Wawrzynek
ICML
2005
IEEE
14 years 8 months ago
Coarticulation: an approach for generating concurrent plans in Markov decision processes
We study an approach for performing concurrent activities in Markov decision processes (MDPs) based on the coarticulation framework. We assume that the agent has multiple degrees ...
Khashayar Rohanimanesh, Sridhar Mahadevan
ISCC
2006
IEEE
154views Communications» more  ISCC 2006»
14 years 2 months ago
Decentralized Load Balancing for Highly Irregular Search Problems
In this paper, we present a Dynamic Load Balancing (DLB) policy for problems characterized by a highly irregular search tree, whereby no reliable workload prediction is available....
Giuseppe Di Fatta, Michael R. Berthold