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GECCO
2005
Springer
232views Optimization» more  GECCO 2005»
14 years 1 months ago
A hardware pipeline for function optimization using genetic algorithms
Genetic Algorithms (GAs) are very commonly used as function optimizers, basically due to their search capability. A number of different serial and parallel versions of GA exist. ...
Malay Kumar Pakhira, Rajat K. De
ISLPED
2003
ACM
122views Hardware» more  ISLPED 2003»
14 years 22 days ago
A mixed-clock issue queue design for globally asynchronous, locally synchronous processor cores
Ever shrinking device sizes and innovative micro-architectural and circuit design techniques have made it possible to have multi-million transistor systems running at multi-gigahe...
Venkata Syam P. Rapaka, Diana Marculescu
JIB
2006
220views more  JIB 2006»
13 years 7 months ago
An assessment of machine and statistical learning approaches to inferring networks of protein-protein interactions
Protein-protein interactions (PPI) play a key role in many biological systems. Over the past few years, an explosion in availability of functional biological data obtained from hi...
Fiona Browne, Haiying Wang, Huiru Zheng, Francisco...
ASPLOS
2012
ACM
12 years 3 months ago
Relyzer: exploiting application-level fault equivalence to analyze application resiliency to transient faults
Future microprocessors need low-cost solutions for reliable operation in the presence of failure-prone devices. A promising approach is to detect hardware faults by deploying low-...
Siva Kumar Sastry Hari, Sarita V. Adve, Helia Naei...
CGO
2008
IEEE
14 years 1 months ago
Prediction and trace compression of data access addresses through nested loop recognition
This paper describes an algorithm that takes a trace (i.e., a sequence of numbers or vectors of numbers) as input, and from that produces a sequence of loop nests that, when run, ...
Alain Ketterlin, Philippe Clauss