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» Performance Modeling and Evaluation of E-Business Systems
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TC
2010
13 years 2 months ago
Architectures and Execution Models for Hardware/Software Compilation and Their System-Level Realization
We propose an execution model that orchestrates the fine-grained interaction of a conventional general-purpose processor (GPP) and a high-speed reconfigurable hardware accelerator ...
Holger Lange, Andreas Koch
WSC
1997
13 years 9 months ago
Using a Simulation Model to Evaluate the Configuration of a Sortation Facility
At a parcel delivery company, the items being shipped must be sorted by destination. However, the company typically serves more destinations than there are distinct positions for ...
Dale Masel, David Goldsmith
3DIC
2009
IEEE
169views Hardware» more  3DIC 2009»
14 years 24 days ago
3-D memory organization and performance analysis for multi-processor network-on-chip architecture
Several forms of processor memory organizations have been in use to optimally access off-chip memory systems mainly the Hard disk drives (HDD). Recent trends show that the solid s...
Awet Yemane Weldezion, Zhonghai Lu, Roshan Weerase...
ASPDAC
2006
ACM
148views Hardware» more  ASPDAC 2006»
14 years 1 months ago
An automated design flow for 3D microarchitecture evaluation
- Although the emerging three-dimensional integration technology can significantly reduce interconnect delay, chip area, and power dissipation in nanometer technologies, its impact...
Jason Cong, Ashok Jagannathan, Yuchun Ma, Glenn Re...
INFOCOM
2010
IEEE
13 years 6 months ago
Coupled 802.11 Flows in Urban Channels: Model and Experimental Evaluation
Abstract—Contending flows in multi-hop 802.11 wireless networks compete with two fundamental asymmetries: (i) channel asymmetry, in which one flow has a stronger signal, potent...
Joseph Camp, Ehsan Aryafar, Edward W. Knightly