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CODES
2009
IEEE
14 years 3 months ago
An on-chip interconnect and protocol stack for multiple communication paradigms and programming models
A growing number of applications, with diverse requirements, are integrated on the same System on Chip (SoC) in the form of hardware and software Intellectual Property (IP). The d...
Andreas Hansson, Kees Goossens
ISSAC
2007
Springer
128views Mathematics» more  ISSAC 2007»
14 years 3 months ago
Productivity and performance using partitioned global address space languages
Partitioned Global Address Space (PGAS) languages combine the programming convenience of shared memory with the locality and performance control of message passing. One such langu...
Katherine A. Yelick, Dan Bonachea, Wei-Yu Chen, Ph...
SC
1995
ACM
14 years 11 days ago
Lazy Release Consistency for Hardware-Coherent Multiprocessors
Release consistency is a widely accepted memory model for distributed shared memory systems. Eager release consistency represents the state of the art in release consistent protoc...
Leonidas I. Kontothanassis, Michael L. Scott, Rica...
HPCA
1999
IEEE
14 years 1 months ago
WildFire: A Scalable Path for SMPs
Researchers have searched for scalable alternatives to the symmetric multiprocessor (SMP) architecture since it was first introduced in 1982. This paper introduces an alternative ...
Erik Hagersten, Michael Koster
IEEEPACT
2007
IEEE
14 years 3 months ago
JudoSTM: A Dynamic Binary-Rewriting Approach to Software Transactional Memory
With the advent of chip-multiprocessors, we are faced with the challenge of parallelizing performance-critical software. Transactional memory (TM) has emerged as a promising progr...
Marek Olszewski, Jeremy Cutler, J. Gregory Steffan