481 search results - page 50 / 97 » Performance Modeling and Measurement of Parallelized Code fo... |
DATE
2008
IEEE
14 years 3 months ago
2008
IEEE
This paper presents a novel cycle-approximate performance estimation technique for automatically generated transaction level models (TLMs) for heterogeneous multicore designs. The...
JPDC
2006
13 years 8 months ago
2006
We describe a new suite of computational benchmarks that models applications featuring multiple levels of parallelism. Such parallelism is often available in realistic flow comput...
ISHPC
1999
Springer
14 years 1 months ago
1999
Springer
On-chip multiprocessor can be an alternative to the wide-issue superscalar processor approach which is currently the mainstream to exploit the increasing number of transistors on ...
SAC
2006
ACM
14 years 2 months ago
2006
ACM
In this paper, we present an efficient procedure for building a piecewise linear function approximation of the speed function of a processor with hierarchical memory structure. Th...
IPPS
2005
IEEE
14 years 2 months ago
2005
IEEE
Parallel random access memory, or PRAM, is a now venerable model of parallel computation that that still retains its usefulness for the design and analysis of parallel algorithms....