481 search results - page 9 / 97 » Performance Modeling and Measurement of Parallelized Code fo... |
HPCA
1999
IEEE
13 years 11 months ago
1999
IEEE
Previous simulators for shared-memory architectures have imposed a large tradeoff between simulation accuracy and speed. Most such simulators model simple processors that do not e...
DDECS
2006
IEEE
14 years 1 months ago
2006
IEEE
—The impact of shared instruction memory on performance is measured and analyzed for an FPGAbased Multiprocessor System-on-Chip (MP-SoC) with an MPEG-4 video encoding application...
IPPS
2007
IEEE
14 years 1 months ago
2007
IEEE
This paper explores generating efficient, portable HighSpeed Producer Consumer (HSPC) code on current shared memory architectures: Chip Multi-Processors (CMP), Simultaneous Multi...
HIPC
1999
Springer
13 years 11 months ago
1999
Springer
Abstract. In this work we put into evidence how the memory performance of a WebServer machine may depend on the sharing induced by process migration. We considered a shared-bus sha...
PACT
2007
Springer
14 years 1 months ago
2007
Springer
Abstract. It has been already verified that hardware-supported finegrain synchronization provides a significant performance improvement over coarse-grained synchronization mecha...