260 search results - page 7 / 52 » Performance Modelling and Optimization of Memory Access on C... |
HPCA
2005
IEEE
14 years 7 months ago
2005
IEEE
Memory system optimizations have been well studied on single-threaded systems; however, the wide use of simultaneous multithreading (SMT) techniques raises questions over their ef...
ICASSP
2011
IEEE
12 years 11 months ago
2011
IEEE
For high-data-rate applications, turbo-like iterative decoders are implemented with parallel hardware architecture. However, to achieve high throughput, concurrent accesses to each...
IPPS
2006
IEEE
14 years 1 months ago
2006
IEEE
UPC’s implicit communication and fine-grain programming style make application performance modeling a challenging task. The correspondence between remote references and communi...
TC
2010
13 years 2 months ago
2010
We propose an execution model that orchestrates the fine-grained interaction of a conventional general-purpose processor (GPP) and a high-speed reconfigurable hardware accelerator ...
EUROPAR
1997
Springer
13 years 11 months ago
1997
Springer
The large latency of memory accesses is a major obstacle in obtaining high processor utilization in large scale shared-memory multiprocessors. Access to remote memory is likely to ...