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» Performance Modelling of the Computational Hardware: A Stati...
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CF
2009
ACM
15 years 11 months ago
Core monitors: monitoring performance in multicore processors
As we reach the limits of single-core computing, we are promised more and more cores in our systems. Modern architectures include many performance counters per core, but few or no...
Paul E. West, Yuval Peress, Gary S. Tyson, Sally A...
ACSC
2004
IEEE
15 years 8 months ago
Exploiting FPGA Concurrency to Enhance JVM Performance
The Java Programming Language has been praised for its platform independence and portability, but because of its slow execution speed on a software Java Virtual Machine (JVM), som...
James Parnis, Gareth Lee
152
Voted
FCCM
2005
IEEE
115views VLSI» more  FCCM 2005»
15 years 10 months ago
FIFO Communication Models in Operating Systems for Reconfigurable Computing
Increasing demands upon embedded systems for higher level services like networking, user interfaces and file system management, are driving growth in fully-featured operating syst...
John A. Williams, Neil W. Bergmann, X. Xie
ICPR
2008
IEEE
16 years 5 months ago
Combine hierarchical appearance statistics for accurate palmprint recognition
Palmprint recognition is an active member of biometrics in recent years. State-of-the-art algorithms of palmprint recognition describe appearances of palmprints efficiently throug...
Tieniu Tan, Yufei Han, Zhenan Sun
GLVLSI
2008
IEEE
147views VLSI» more  GLVLSI 2008»
15 years 11 months ago
Statistical timing analysis of flip-flops considering codependent setup and hold times
Statistical static timing analysis (SSTA) plays a key role in determining performance of the VLSI circuits implemented in state-of-the-art CMOS technology. A pre-requisite for emp...
Safar Hatami, Hamed Abrishami, Massoud Pedram