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DATE
2005
IEEE
143views Hardware» more  DATE 2005»
13 years 11 months ago
Statistical Modeling of Pipeline Delay and Design of Pipeline under Process Variation to Enhance Yield in sub-100nm Technologies
Operating frequency of a pipelined circuit is determined by the delay of the slowest pipeline stage. However, under statistical delay variation in sub-100nm technology regime, the...
Animesh Datta, Swarup Bhunia, Saibal Mukhopadhyay,...
SBACPAD
2008
IEEE
170views Hardware» more  SBACPAD 2008»
14 years 3 months ago
Using Analytical Models to Efficiently Explore Hardware Transactional Memory and Multi-Core Co-Design
Transactional memory is emerging as a parallel programming paradigm for multi-core processors. Despite the recent interest in transactional memory, there has been no study to char...
James Poe, Chang-Burm Cho, Tao Li
ICCD
2004
IEEE
106views Hardware» more  ICCD 2004»
14 years 6 months ago
A New Statistical Optimization Algorithm for Gate Sizing
— In this paper, we approach the gate sizing problem in VLSI circuits in the context of increasing variability of process and circuit parameters as technology scales into the nan...
Murari Mani, Michael Orshansky
ICPR
2010
IEEE
14 years 3 months ago
Automatic Pathology Annotation on Medical Images: A Statistical Machine Translation Framework
Large number of medical images are produced daily in hospitals and medical institutions, the needs to efficiently process, index, search and retrieve these images are great. In t...
Tianxia Gong, Shimiao Li, Chew-Lim Tan, Boon Chuan...
ACL
2010
13 years 7 months ago
Training Phrase Translation Models with Leaving-One-Out
Several attempts have been made to learn phrase translation probabilities for phrasebased statistical machine translation that go beyond pure counting of phrases in word-aligned t...
Joern Wuebker, Arne Mauser, Hermann Ney