— In this paper we evaluate, by means of Extrinsic Information Transfer (EXIT) charts, an iterative receiver that has emerged as a promising candidate for non-coherent multi-user...
Peter Hammarberg, Fredrik Rusek, Pierluigi Salvo R...
As semiconductor feature sizes decrease, interconnect delay is becoming a dominant component of processor cycle times. This creates a critical need to shift microarchitectural des...
Dynamically reconfigurable systems based on partial and dynamically reconfigurable FPGAs may have their functionality partially modified at run-time without stopping the operation...
Manuel G. Gericota, Gustavo R. Alves, Miguel L. Si...
Gaussian Cubes (GCs) are a family of interconnection topologies in which the interconnection density and algorithmic efficiency are linked by a common parameter, the variation of ...
- Even though state-of-the-art FPGAs present new opportunities in exploring low-cost high-performance architectures for floating-point scientific applications, they also pose serio...