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» Performance Prediction of a Parallel Simulator
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ISCA
2006
IEEE
148views Hardware» more  ISCA 2006»
14 years 2 months ago
Tolerating Dependences Between Large Speculative Threads Via Sub-Threads
Thread-level speculation (TLS) has proven to be a promising method of extracting parallelism from both integer and scientific workloads, targeting speculative threads that range ...
Christopher B. Colohan, Anastassia Ailamaki, J. Gr...
ASAP
2005
IEEE
121views Hardware» more  ASAP 2005»
14 years 2 months ago
Using TLM for Exploring Bus-based SoC Communication Architectures
As billion transistor System-on-chips (SoC) become commonplace and design complexity continues to increase, designers are faced with the daunting task of meeting escalating design...
Sudeep Pasricha, Mohamed Ben-Romdhane
IEEEPACT
2005
IEEE
14 years 2 months ago
A Distributed Control Path Architecture for VLIW Processors
VLIW architectures are popular in embedded systems because they offer high-performance processing at low cost and energy. The major problem with traditional VLIW designs is that t...
Hongtao Zhong, Kevin Fan, Scott A. Mahlke, Michael...
GECCO
2005
Springer
189views Optimization» more  GECCO 2005»
14 years 1 months ago
Molecular programming: evolving genetic programs in a test tube
We present a molecular computing algorithm for evolving DNA-encoded genetic programs in a test tube. The use of synthetic DNA molecules combined with biochemical techniques for va...
Byoung-Tak Zhang, Ha-Young Jang
ICN
2005
Springer
14 years 1 months ago
Scheduling Algorithms for Input Queued Switches Using Local Search Technique
Input Queued switches have been very well studied in the recent past. The Maximum Weight Matching (MWM) algorithm is known to deliver 100% throughput under any admissible traffic. ...
Yanfeng Zheng, Simin He, Shutao Sun, Wen Gao