372 search results - page 17 / 75 » Performance Studies of a Parallel Prolog Architecture |
ICCD
2005
IEEE
16 years 8 days ago
2005
IEEE
The formal analysis of parallelism and pipelining is performed on an 8-bit Add-Compare-Select element of a Viterbi decoder. The results are quantified through a study of the delay...
122
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ICS
2009
Tsinghua U.
15 years 10 months ago
2009
Tsinghua U.
Iterative stencil loops (ISLs) are used in many applications and tiling is a well-known technique to localize their computation. When ISLs are tiled across a parallel architecture...
122
Voted
PDP
1996
IEEE
15 years 7 months ago
1996
IEEE
A case study of performance and dependability evaluation of fault-tolerant multiprocessors is presented. Two specific architectures are analyzed taking into account system functio...
126
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ICPPW
2002
IEEE
15 years 8 months ago
2002
IEEE
This paper presents a methodology for aiding a scientific programmer to evaluate the performance of parallel programs on advanced architectures. It applies well-defined design o...
152
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ISCA
2009
IEEE
15 years 10 months ago
2009
IEEE
With the shift towards chip multiprocessors (CMPs), exploiting and managing parallelism has become a central problem in computer systems. Many issues of parallelism management boi...