Sciweavers

372 search results - page 29 / 75
» Performance Studies of a Parallel Prolog Architecture
Sort
View
EUROPAR
2006
Springer
14 years 5 days ago
Optimization of Dense Matrix Multiplication on IBM Cyclops-64: Challenges and Experiences
Abstract. This paper presents a study of performance optimization of dense matrix multiplication on IBM Cyclops-64(C64) chip architecture. Although much has been published on how t...
Ziang Hu, Juan del Cuvillo, Weirong Zhu, Guang R. ...
DAGM
2008
Springer
13 years 10 months ago
Sliding-Windows for Rapid Object Class Localization: A Parallel Technique
Abstract. This paper presents a fast object class localization framework implemented on a data parallel architecture currently available in recent computers. Our case study, the im...
Christian Wojek, Gyuri Dorkó, André ...
PLDI
1995
ACM
14 years 1 days ago
Improving Balanced Scheduling with Compiler Optimizations that Increase Instruction-Level Parallelism
Traditional list schedulers order instructions based on an optimistic estimate of the load latency imposed by the hardware and therefore cannot respond to variations in memory lat...
Jack L. Lo, Susan J. Eggers
TROB
2002
120views more  TROB 2002»
13 years 8 months ago
DPAC: an object-oriented distributed and parallel computing framework for manufacturing applications
Parallel and distributed computing infrastructure are increasingly being embraced in the context of manufacturing applications, including real-time scheduling. In this paper, we pr...
N. R. Srinivasa Raghavan, Tanmay Waghmare
IPPS
2006
IEEE
14 years 2 months ago
Platform-based FPGA architecture: designing high-performance and low-power routing structure for realizing DSP applications
The novel design of an efficient FPGA interconnection architecture with multiple Switch Boxes (SB) and hardwired connections for realizing data intensive applications (i.e. DSP ap...
Kostas Siozios, Konstantinos Tatas, Dimitrios Soud...