618 search results - page 53 / 124 » Performance and energy optimization of concurrent pipelined ... |
MICRO
2003
IEEE
14 years 1 months ago
2003
IEEE
This paper proposes and evaluates single-ISA heterogeneous multi-core architectures as a mechanism to reduce processor power dissipation. Our design incorporates heterogeneous cor...
ACMSE
2004
ACM
14 years 1 months ago
2004
ACM
Modern processors include features such as deep pipelining, multilevel cache hierarchy, branch predictors, out of order execution engine, and advanced floating point and multimedi...
DATE
2005
IEEE
14 years 1 months ago
2005
IEEE
In today’s embedded applications a significant portion of energy is spent in the memory subsystem. Several approaches have been proposed to minimize this energy, including the u...
PE
2007
Springer
13 years 7 months ago
2007
Springer
To develop simple traffic engineering rules for the downlink of a cellular system using Proportional Fairness (PF) scheduling, we study the “strict” and “approximate” ins...
CASES
2006
ACM
14 years 1 months ago
2006
ACM
In this paper, we propose a fully automatic dynamic scratchpad memory (SPM) management technique for instructions. Our technique loads required code segments into the SPM on deman...